Intel announced today that it will delay the launch of its forthcoming quad-core Itanium processor, codenamed Tukwila, in order to give the overall Itanium platform a big boost in the memory department.
You may recall Intel's unveiling of its next-generation, quad-core Itanium chip at last year's ISSCC, where I asked in our coverage: "What rhymes with 'Godzilla,' weighs 2 billion transistors, and has enough on-die cache to take out Tokyo?" Tukwila, as the part is codenamed, is a seriously big chip, especially on the 65nm process on which it will debut. Check out the chart above for wattage numbers for the 21.5x32.5mm2 part.
Tukwila was supposed to be out before the end of the year, and now it's being pushed back even further due to validation issues. But the validation delay is related not to the chip, but to the Itanium platform, and in particular to enhancements that will enable the platform to host much more DDR3 memory than it otherwise could.
Specifically, Intel has announced that the forthcoming platform version will feature a "scalable memory buffer" that sits on the four DDR3 channels that run between the CPU's integrated memory controller and the DIMM banks. This buffer will enable expanded memory capacities (how much, Intel won't say), so that Tukwilla will be able to hold much more buffered memory than it could otherwise.
My initial reaction on hearing about the buffer was that Intel was simply using the DDR3 version of technology from MetaRAM. Intel demoed a 16GB DIMM using MetaRAM tech this past summer, and MetaRAM counts Intel Capital among is prominent investors, so this seemed like a no-brainer. I'm glad I double-check, though, because Intel was quite clear that what Tukwila is using is not the MetaRAM DDR3 module.
Rather, the new buffer takes the form of a discrete, Intel-designed "buffer-on-board" (BoB) module that can be placed either directly on the motherboard or onto a memory riser card; the choice is up to the motherboard maker.
Regular DDR3 can be used with BoB, so the technology provides for full compatibility with existing memory modules.
If this notion of putting a discrete buffer module in between a processor's on-die memory controller and a bank of DDR3 sounds familiar to you, it should. Back in the summer of 2007, AMD announced that its Socket G3 Memory Extender (G3MX) microbuffer technology would soon make its way onto AMD's server platform, doubling or quadrupling the amount of DDR3 memory that the platform could host.
In the wake of AMD's announcement, the Inquirer reported that Intel was also working on a similar microbuffer technology to replace FB-DIMM, and would announce it shortly. But AMD's G3MX plans promptly went nowhere—the effort seems to have been cancelled—leaving Intel to wring the last drops out of FB-DIMM in 2008 before bowing to the inevitability that is DDR3. The BoB discussed today would appear to be the long-rumored, Intel-designed microbuffer FB-DIMM replacement, and Intel will be saying more about it at Spring IDF.
Source: ars technica
