Chips made using the currently available technology are faced with two major problems that limit their scalability. The first is coordination. As chip densities grow beyond 16 cores, it becomes increasingly difficult to synchronize their operation so that they work in harmony. The second challenge is power consumption. As processing capacity grows, it takes more and more energy to move data in and out of memory.
The Corona solution addresses both these problems. It will use light-based integrated photonics to interlink the cores optically. This is both fast and consumes very little power. HP estimates that to transfer data at speeds of 10 terabytes per second between the CPU and memory would require only 6.4W of power as compared to 160W needed for conventional silicon-based solutions.
It also will leverage a stacking technology known as TSV (through silicon vias). Today's cores are laid out next to each other in a flat configuration. TSV literally stacks multiple cores one on top of each other. This both saves space and shortens the path between cores, allowing for faster communications and energy efficiency. HP plans to have its 256 cores organized in 64 four-core clusters.
There are still several barriers that have to be overcome before the Corona can actually be built. A key one is manufacturing technology. The chip will be built using a 16-nanometer manufacturing process, which for HP won't be available for five years.
