NVIDIA is involved in a bid to create a graphics chip for a supercomputer by 2018 and has described the device at the Supercomputing 2010 show. Three other teams are involved in the race that is funded by the US Department of Defense. NVIDIA's project, called Echelon, would mostly advance through its use of memory on many cores. The chip will have 256MB of SRAM that can be dynamically configured based on an app's requirements.
It could, for example, be broken down into as many as six levels of cache, each of a different size. Each would have its own cache, with the goal to bring data close to the processing elements to reduce the distance it needs to travel.
Intel, MIT and Sandia National Labs will compete with NVIDIA in the Ubiquitous High Performance Computing program, sponsored by DARPA. DARPA requires a prototype petaflop-class system in a 57-kilowatt rack by 2014, with the systems potentially used as parts of an exascale system with a target date of 2018.
"If you can do a really good job computing at one scale you can do it at another," said Bill Dally, NVIDIA's chief scientist in charge of Echelon. Lessons learned in the development of this chip will translate to consumer products then, with Dally stressing that NVIDIA focuses on a performance-per-watt ratio for all its products.
Dally talked about a graphics core that can process a floating point operation with just 10 picojoules of energy. In comparison, a current Fermi chip uses 200 picojoules. Eight such cores would make up a streaming multiprocessor and 128 of them would create a chip. Eventually, a 1,000-core graphics chip would have an equivalent performance of 10 teraflops per chip, where each core can handle four double precision floating-point operations per clock cycle.
Eight-core chips would power future handsets, Dally said.
Echelon is just in the paper design stage with simulations, so is subject to plenty of changes before 2018 arrives.
