Processor industry watchers who have been waiting for the Intel Developer Forum because they're dying for a deep dive on the microarchitectural details of the company's 32nm Sandy Bridge architecture are still waiting. Intel's top brass delivered more jargon and eye candy than they did technical dirt, but Sandy Bridge is still worth talking about in light of Intel's keynote. And then there's the Tunnel Creek announcement, which sees Intel taking aim right at the embedded market.
The 32nm process node marks the first time that Intel can fit many of the main parts of a PC on a single slice of silicon. The first Sandy Bridge parts will integrate four CPU cores, a GPU, and northbridge hardware (display, I/O, and a memory controller) onto a single piece of silicon. (I didn't bring a camera to the keynote, so you'll have to hit Anandtech for pictures.) This is indeed a major milestone for the PC, and it will make Sandy Bridge-based systems faster and cheaper than even their 32nm predecessors.
The few solid Sandy Bridge details that Intel has confirmed so far is that all of the major blocks on the chip—the CPU cores, the GPU, and the northbridge—will be connected by a high-bandwidth ring bus, and they'll all share a common L3 cache.
We saw this ring bus first with Larrabee, where Intel used it to link the part's x86 cores together. It's very fast and relatively simple, but also fairly power hungry when compared to, say, switched tiles. Overall though, it's sure to be a good fit for the low core count that Intel is targeting with this generation.
The fact that the CPU and GPU are not only connected so closely, but also share a common L3 cache, is no doubt a major factor in Sandy Bridge's stellar graphics performance. Some early preview numbers show that Sandy Bridge's integrated graphics performance is very, very good compared to the other IGP options on the market. The Sandy Bridge GPU even gives some of the entry-level discrete graphics cards a run for their money.
The ability to bundle this level of graphics performance on a quad-core CPU die is, again, a major milestone for the PC, and it will significantly drive down costs and platform-level power consumption. Large IT buyers will especially love this, because they'll finally get best-in-class IGP performance by default on all of their machines, and (eventually) for less money.
Up Tunnel Creek
While Sandy Bridge's ring bus and shared L3 were yesterday's news, Intel today formally announced the Atom E600 system on a chip (SoC), codenamed Tunnel Creek.
As we pointed out in our previous coverage of the part, what's special about Tunnel Creek is that it combines a CPU, GPU, memory controller, and PCIe bus on the same chip. The presence of the PCIe bus in particular is important, because it lets the part gluelessly integrate with a whole host of application-specific circuits. In other words, many integrated circuits that you would want to use in an embedded system talk PCIe, and for a normal Moorestown part you'd need an I/O hub chip in between that IC and the main SoC. This isn't the case with Tunnel Creek, however, because it speaks PCIe natively.
A great example of this is an Atom-based NAS box. With the Atom E600, the main SoC could talk directly to the RAID controller on the PCIe bus, without going through a bridge chip. By cutting out the extra chip, the NAS would be cheaper, cooler, and more reliable.
While Intel's press kit on the E600 talks up the part's potential as the basis for an in-car infotainment platform, Intel has also mentioned that it is targeting the Chinese telecom market with this chip—the company is hoping to get a slice of the Chinese telecom build-out that the country is undertaking to stimulate its economy.
Source: ars technica
