The next-generation DDR4 SDRAM memory will bring rather ultimate performance improvements to both desktops and laptops as well as servers and workstations. But the new performance heights will demand a rather radical change to topology of memory sub-system.
At a recent MemCon conference in Tokyo, Japan, Bill Gervasi, vice president of engineering at US Modular and a member of the JEDEC board of directors, revealed that the target effective clock-speeds for DDR4 memory would be 2133MHz - 4266MHz, an increase from previously discussed frequencies. Apparently, JEDEC and memory manufacturers decided that the progress of DDR3 leaves no space for DDR4 data rates below 2133Mb/s.
The designers of DDR4 memory are looking forward 1.2V and 1.1V voltage settings for the new memory type and are even considering 1.05V option to greatly reduce power consumption of the forthcoming systems. It is expected that manufacturers of dynamic random access memory (DRAM) will have to use advanced fabrication technology to make the DDR4 chips. The first chips are likely to be made using 32nm or 36nm process technologies.
At present JEDEC expects to finalize the DDR4 specification in 2011 and start commercial production in 2012. Actual mass transition to the next-generation memory is projected to occur towards 2015.
But extreme performance will require a tradeoff. In DDR4 memory sub-systems every memory channel will only support one memory module, reports PC Watch web-site, since the developers substituted current multi-drop bus in facour of point-to-point topology. In order to overcome potential inability to install appropriate amount of memory into high-end clients as well as servers, the developers have reportedly presented two approaches:
- DRAM manufacturers will need to dramatically increase capacities of memory chips by using multi-layer technique with through silicon via (TSV) technology. As a result, DDR4 memory chips with very high density will become relatively inexpensive. Obviously, this will naturally make memory upgrades slightly more complicated as in order to sustain multi-channel memory performance, all memory modules will have to replaced with more advanced DIMMs.
- In case of server multi-layer DRAM IC approach only will not be viable for high-end machines. As a result, it is proposed that special switches are installed onto mainboards to allow multiple memory modules to work on a single memory channel.
The transition to DDR3 memory has taken a long time already and will take a couple more years to complete. But the transition to DDR4 memory will take even longer since it will be much more complicated for all the participants of the ecosystem: the DRAM chip makers, memory module manufacturers, mainboard makers, microprocessor producers, system builders and end-users.
