16- and 48-core monster chips on tap at next week's ISSCC

Intel, IBM, Sun, AMD, and other chipmakers are set to unveil the details of a host of present and future processor designs at this year's International Solid State Circuits Conference. Let's take a look at each company's sessions, which cover processors that range from single-core to 48 cores, in turn.

Sun's SPARC burns on, AMD goes 32nm

Despite the recent closing of its acquisition by Oracle and Thursday's resignation of CEO Jonathan Schwartz, Sun is keeping up appearances that work on the SPARC family of processors will continue, at least in the near term. The company has a session on its 40nm, 16-core, 128-thread Niagara processor, which is aimed at glueless, four-socket systems.

Sun's talk looks like it will focus mainly on power and process issues, so I'm not sure how much microarchitectural detail we'll get. I'll be hitting the session, though, because who knows what will happen to the SPARC line now that Oracle is running the show. This could be the last major new chip reveal from Sun.

AMD is set to describe an upcoming 32nm mobile processor that may be either the Bobcat part revealed in November of last year, or the company's first "Fusion" processor, codenamed Llano. What follows is the very brief, cryptic program description:

The 32nm implementation of an AMD x86-64 core occupying 9.69mm2 and containing more than 35 million transistors (excluding L2 cache), operates at frequencies >3GHz. The core incorporates numerous design and power improvements to enable an operating range of 2.5 to 25W and a zero-power gated state that make the core well-suited to a broad range of mobile and desktop products.

The fact that the core is only 35 million transistors (in the ballpark with Atom) strongly indicates to me that it's Bobcat, but Bobcat is designed for sub-1W applications. This chip, on the other hand, is said to scale from 2.5 to 25 watts, which suggests that it may be Llano. Still, it's not clear to me how they packed a usable processor core and GPU into that thin transistor budget. So my money is on a Bobcat reveal.

Intel talks Westmere, 48-core monster

Intel has been briefing folks on Westmere, the company's 32nm shrink of the Nehalem architecture, under NDA for some time now. But the big public reveal comes in a Monday session. Westmere is actually more than a straight shrink of Nehalem from 45nm to 32nm—it brings some new features and instructions, all of which Intel will detail in this session.

Note that Intel recently launched the first round of its Westmere products, in the form of the desktop-oriented Clarksdale and the mobile-oriented Arrandale chips. The company will launch its higher-end, six-core Gulftown processor later this year, possibly as soon as March. (If you're confused by the Intel codenames, take a look at the decoder chart below).

Also on tap are further details about Intel's experimental 48-core processor, the Single-Chip Cloud Computer (SCCC). Little is currently known about the individual cores that make up the SCCC, other than that each is a full x86 implementation that's capable of running its own OS instance. Each core is probably fairly simple, but that's fine, because SCCC is still just a prototype. At some point, Intel will productize something like SCCC, so right now the chip is a good testbed for trying out different hardware and software techniques for getting performance out of what is essentially a network-on-a-chip.

Finally, Intel will launch its long, long, long-delayed "Tukwila" Itanium processor on Monday, a 65nm, 2,000,000,000-transistor monster that was behind schedule back when Intel showed it off at ISSCC 2008. I expect the Last Trump to sound shortly after the launch event is concluded.


Going head-to-head with Intel's Tukwila launch on Monday is IBM's big POWER7 unveiling, where the company will offer a session on its 8-core, 32-thread server processor. We'll learn the microarchitectural details of POWER7, which I hear has considerable similarities to the POWER4/970 processor family that I devoted a portion of my book to.

IBM is also giving a session on a 16-core, 32-thread processor that I haven't heard of before. Below is the session information:

5.5 A Wire-Speed PowerTM Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads 3:45 PM

A 64-thread simultaneous multi-threaded processor uses architecture and implementation techniques to achieve high throughput at low power. Included are static VDD scaling, multi-voltage design, clock gating, multiple VT devices, dynamic thermal control, eDRAM and low-voltage circuit design. Power is reduced by >50% in a 428mm2 chip. Worst-case power is 65W at 2.0GHz, 0.85V.

I have no idea what this chip is for, so if you know something about it, please drop me a line.

In all, this is one of the more exciting ISSCCs in recent years. And unfortunately, it may be the last exciting one for a while, what with semiconductor R&D budgets having been so brutally slashed in the downturn. All of the aforementioned products represent work that was in the pipeline before the financial crisis hit in 2008, so it's likely that there's a pipeline "bubble" coming (to borrow a CPU metaphor) in 2011.

Source: ars technica

Tags: AMD, CPUs, IBM, Intel, Sun

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