The PCI-SIG has made available the feature complete PCIe 5.0, Version 0.9 to members, satying on target to publish PCIe 5.0, Version 1.0 in the first quarter of 2019.
In 2017, PCI-SIG delivered PCI Express 4.0 with its 16 GT/s, while also diving headfirst into PCI Express 5.0 development – first announced at our annual PCI-SIG DevCon in June 2017. The publication of the feature complete PCIe 5.0, Version 0.9 is an indicator that PCI-SIG will be able to meet its goal of doubling bandwidth—from 16 GT/S to 32 GT/s—in a record less than two years.
PCIe 5.0 delivers a speed upgrade that will reach a data rate of 32 GT/s and offer adaptable lane configurations, while maintaining a low power envelope. The new spec builds off of PCIe 4.0, which already supports higher speeds via extended tags and credits. The PCIe 5.0 specification touts a variety of features, such as electrical changes to improve signal integrity and mechanical performance of connectors; CEM connector targeted to be backwards compatible for add-in cards; and backward compatibility with PCIe 4.0, 3.x, 2.x and 1.x.
